MLK-23159-9 arm64: dts: freescale: Add i.MX8MP basic DT support

Add i.MX8MP SoC & board basic DT support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Ella Feng<ella.feng@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

1 files changed, 476 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
new file mode 100644
index 000000000000..2f673991710a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+
+/ {
+	model = "FSL i.MX8MP EVK";
+	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		status {
+			label = "status";
+			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			default-state = "on"; /* LED GREEN */
+		};
+	};
+
+	tcm@00800000 {
+		compatible = "fsl,tcm";
+		reg = <0x0 0x00800000 0 0x1000>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: regulator-usdhc2 {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			startup-delay-us = <100>;
+			off-on-delay-us = <12000>;
+		};
+
+		reg_can1_stby: regulator-can1-stby {
+			compatible = "regulator-fixed";
+			regulator-name = "can1-stby";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_flexcan1_reg>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_can2_stby: regulator-can2-stby {
+			compatible = "regulator-fixed";
+			regulator-name = "can2-stby";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_flexcan2_reg>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mp-evk {
+
+		pinctrl_flexcan1_reg: flexcan1reggrp {
+			fsl,pins = <
+				MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x154	/* CAN1_STBY */
+			>;
+		};
+
+		pinctrl_flexcan2_reg: flexcan2reggrp {
+			fsl,pins = <
+				MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x154	/* CAN2_STBY */
+			>;
+		};
+
+		pinctrl_fec: fecgrp {
+			fsl,pins = <
+				MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
+				MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
+				MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
+				MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
+				MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
+				MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
+				MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
+				MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
+				MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
+				MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
+				MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
+				MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
+				MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
+				MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+				MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
+			>;
+		};
+
+		pinctrl_gpio_led: gpioledgrp {
+			fsl,pins = <
+				MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+				MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
+				MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
+				MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
+				MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
+				MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
+				MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
+				MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
+				MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_pmic: pmicirq {
+			fsl,pins = <
+				MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
+				MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
+				MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
+				MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
+				MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
+				MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
+				MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
+				MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
+				MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
+				MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
+				MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
+				MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
+				MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
+				MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
+				MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
+				MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 	0x1c4
+				MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
+				MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
+				MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
+				MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
+				MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
+				MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
+				MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
+				MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
+				MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
+				MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
+				MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
+				MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
+				MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+			fsl,pins = <
+				MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
+				MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
+				MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
+				MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
+				MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
+				MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
+				MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
+				MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
+				MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
+				MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
+				MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
+				MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
+				MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
+				MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
+				MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
+				MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
+				MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+			fsl,pins = <
+				MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
+				MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
+				MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
+				MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
+				MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
+				MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
+				MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
+				MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
+				MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
+				MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
+				MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+			fsl,pins = <
+				MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
+				MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
+				MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
+				MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
+				MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
+				MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
+				MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
+				MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
+				MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
+				MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
+				MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
+			>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			eee-broken-1000t;
+			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart1 { /* BT */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart2 {
+	/* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pca9450@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450";
+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9450,pmic-buck2-uses-i2c-dvs;
+			/* Run/Standby voltage */
+			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
+};