diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-27 10:11:08 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-06-24 10:00:28 +0800 |
| commit | 1bda33273eccae3c0d878d34660eca9da1765db0 (patch) | |
| tree | 319e6e9093d8cdd45d9eb1359f0db343167562d0 /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | 30f393c50b1ba2b1ddde847f280e724534a0a2fb (diff) | |
MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9175639d6e45..652ff82b4466 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1936,7 +1936,7 @@ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <3>; + fsl,max-link-speed = <2>; power-domains = <&pcie_pd>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIEPHY_PERST>, |