diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2020-11-16 11:25:59 +0800 |
|---|---|---|
| committer | Fancy Fang <chen.fang@nxp.com> | 2020-11-19 13:51:02 +0800 |
| commit | 1e1f957cda193ece9346f0ef39a95bc52a2877ae (patch) | |
| tree | 7932b20d9c5ceb00ea4fa003cabe59659c9c9a4b /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | 5fb6a0554e12dd8bb67ee5b760144f65db6f6f16 (diff) | |
MLK-24998-4 drm/bridge: sec-dsim: use 12MHz for default PHY REF clock
After using osc_24m for MIPI PHY reference clock source,
the default PHY reference clock rate should be changed
also accordingly. Here choose 12MHz rate for this since
below usual DSI output DDR clock rates can be derived
from 12MHz reference:
891000,
810000,
792000,
648000,
472500,
445500,
390000,
297000,
240000,
189000,
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit b3a420c9cf3fe40c408d4eb58841a0d047c186a4)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
0 files changed, 0 insertions, 0 deletions