diff options
| author | Mirela Rabulea <mirela.rabulea@nxp.com> | 2020-03-06 22:14:56 +0200 |
|---|---|---|
| committer | Oliver Brown <oliver.brown@nxp.com> | 2020-04-08 10:32:22 -0500 |
| commit | 636de0a39e2394ac23c261b67dcd7d2ed9128deb (patch) | |
| tree | 5bf4b2655742a6ca4914d1f408a8397ca7507496 /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | 0ed47dbc11b07ff4a7eabe27307bcd552b5ffd44 (diff) | |
MLK-23728: Add ov2775 dtb for imx8mp
Make sure all the needed clocks are enabled for mipi_csi,
do not rely on mipi_dsi or lcdif to enable them.
Needed: media_cam1_pix, media_axi_root, media_apb_root
Tested with VSI ISP demo.
Not tested with camera on CSI2.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Tested-by: Oliver Brown <oliver.brown@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 94b684762905..180a57c0c00f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1723,6 +1723,10 @@ }; }; + mediamix_gpr: media_gpr@32ec0008 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0008 0x4>; + }; cameradev: camera { compatible = "fsl,mxc-md", "simple-bus"; #address-cells = <1>; @@ -1787,14 +1791,16 @@ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; - clock-names = "mipi_clk", "disp_axi", "disp_apb"; + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "mipi_clk", "axi_root", "apb_root"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; assigned-clock-rates = <500000000>; bus-width = <4>; csi-gpr = <&mediamix_gasket0>; + csi-gpr2 = <&mediamix_gpr>; + gpr = <&mediamix_blk_ctl>; no-reset-control; power-domains = <&mipi_phy1_pd>; status = "disabled"; @@ -1804,16 +1810,18 @@ compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; reg = <0x32e50000 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <266000000>; + clock-frequency = <500000000>; clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; - clock-names = "mipi_clk", "disp_axi", "disp_apb"; + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "mipi_clk", "axi_root", "apb_root"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <266000000>; + assigned-clock-rates = <500000000>; bus-width = <4>; csi-gpr = <&mediamix_gasket1>; + csi-gpr2 = <&mediamix_gpr>; + gpr = <&mediamix_blk_ctl>; no-reset-control; power-domains = <&mipi_phy2_pd>; status = "disabled"; |