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authorFancy Fang <chen.fang@nxp.com>2020-04-08 15:34:54 +0800
committerFancy Fang <chen.fang@nxp.com>2020-04-08 15:53:24 +0800
commit639f4b020f43a6e852a28803a8cd252e78d2d822 (patch)
tree0416b6d60493332edb05cc4934238ee84b21f345 /arch/arm64/boot/dts/freescale/imx8mp.dtsi
parentb4b240ce1d2f18889bf2ad642f15a692c8f16dbe (diff)
MLK-23758 arm64: dts: imx8mp: add power domains for dsi, lcdif1 and lcdif2
Add the corresponding power domains for MIPI DSI, LCDIF1 and LCDIF2 device nodes. Signed-off-by: Fancy Fang <chen.fang@nxp.com> Reviewed-by: G.n. Zhou <guoniu.zhou@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp.dtsi3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 0e93ca70b676..94b684762905 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1415,6 +1415,7 @@
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
assigned-clock-rates = <594000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mipi_phy1_pd>;
status = "disabled";
port@0 {
@@ -1442,6 +1443,7 @@
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
blk-ctl = <&mediamix_blk_ctl>;
+ power-domains = <&mediamix_pd>;
status = "disabled";
lcdif_disp0: port@0 {
@@ -1470,6 +1472,7 @@
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1039500000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mediamix_pd>;
status = "disabled";
lcdif2_disp: port@0 {