diff options
author | Laurentiu Palcu <laurentiu.palcu@nxp.com> | 2019-11-26 13:09:22 +0200 |
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committer | Laurentiu Palcu <laurentiu.palcu@nxp.com> | 2019-11-26 13:58:18 +0200 |
commit | 7fbde092c2f784dac6f5a57fc64bf1bda10c031c (patch) | |
tree | 9074d20684554c3ed782d9c070f95033f43eb894 /arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts | |
parent | daa3cebcd9c5b662879f55e0718dfacf6b1e274e (diff) |
arm64: dts: imx8mq: add adv7535 related DTS files
This patch adds:
* an ADV7535 entry in imx8mq-evk.dts;
* DTS for DCSS + MIPI_DSI + ADV7535;
* DTS for LCDIF + MIPI_DSI + ADV7535;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts new file mode 100644 index 000000000000..d98d6dc34f55 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +/delete-node/ &hdmi; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; |