diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2020-05-18 11:14:15 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2020-05-18 13:29:44 +0800 |
| commit | ed9e9c7312af5b5692f83b2475e5a734164bc343 (patch) | |
| tree | f9645ef845844cb83fb17ec032ef898fb87f797c /arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts | |
| parent | 7ef35dc3f999e1ec187e642a070da78b32299130 (diff) | |
MLK-24054 arm64: dts: imx8mq-evk: enable usdhc2 bus on M.2 interface
By default, usdhc2 is for SD boot.
The patch is to enable usdhc2 on M.2 interface for SDIO wlan,
then it requires users use eMMC boot instead of SD boot.
The HW rework:
- install R1429 - R1436
- remove R1617 - R1621, R1603
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts new file mode 100644 index 000000000000..33d7dc1a047f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + mmc-pwrseq = <&usdhc2_pwrseq>; +}; |