MLK-25349-2 arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit d9f9d0c73d3965e6a7b130e2b762a8ff7d4f04a7)
(cherry picked from commit 6430191c9f1e833284ce4cc5915d3fe26c38b024)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 616863fc2d31..4d4ad6021a46 100755
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -670,6 +670,7 @@
 				 <&clk IMX8MQ_SYS2_PLL_100M>,
 				 <&clk IMX8MQ_SYS2_PLL_250M>;
 	hard-wired = <1>;
+	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };
 
@@ -690,6 +691,7 @@
 	assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>,
 				 <&clk IMX8MQ_SYS2_PLL_100M>,
 				 <&clk IMX8MQ_SYS2_PLL_250M>;
+	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };