diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2019-11-28 17:50:54 +0200 |
|---|---|---|
| committer | Robert Chiras <robert.chiras@nxp.com> | 2019-11-28 18:01:08 +0200 |
| commit | 0785deb8657ce501b25ac8206152ada9318192f7 (patch) | |
| tree | 654ad67ac6ae3505fb56f996682005fe34c6e828 /arch/arm64/boot/dts/freescale/imx8mq.dtsi | |
| parent | 7dc82fecec259ec490654e42a01181c1633448a1 (diff) | |
arm64: dts: imx8mq: Add lcdif clock in mipi dsi node
This clock is needed in order to be able to correctly use the MIPI
resets, since this clock is the only one connected to the MIPI Reset
Synchronizer block.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 6bd0f742d1d0..f71ffd231109 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -986,12 +986,14 @@ <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_VIDEO_PLL1>; + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_LCDIF_PIXEL>; clock-names = "core", "rx_esc", "tx_esc", "phy_ref", - "video_pll"; + "video_pll", + "lcdif"; assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, <&clk IMX8MQ_CLK_DSI_CORE>, <&clk IMX8MQ_CLK_DSI_AHB>, |