diff options
| author | Laurentiu Palcu <laurentiu.palcu@nxp.com> | 2019-09-05 13:14:52 +0300 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:44 +0800 |
| commit | 5e64b0716eb1222927972900a0f32ff85b28b11f (patch) | |
| tree | 73088be1aae102111925314926a3064e059a7def /arch/arm64/boot/dts/freescale/imx8mq.dtsi | |
| parent | 06cadee5853b268ee31404feee50dd79d1f681b1 (diff) | |
arm64: dts: imx8mq: add dcss, hdmi and create imx8mq-evk-hdmi.dts file
This will allow using DCSS with HDMI on iMX8MQ.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
[ Aisheng: fix one unnecessary blank line ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c9b89ba85439..b2342a973e1e 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1165,6 +1165,17 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + hdmi: hdmi@32c00000 { + compatible = "cdn,imx8mq-hdmi"; + reg = <0x32c00000 0x100000>; + + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + + lane-mapping = <0xe4>; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; @@ -1176,6 +1187,34 @@ interrupt-controller; #interrupt-cells = <1>; }; + + dcss: dcss@0x32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2D000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", + "dtrc", "pll_src", "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; }; gpu: gpu@38000000 { |