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authorRobin Gong <yibin.gong@nxp.com>2019-04-23 15:40:57 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:04:14 +0800
commit8877af4ee506a3421ece35e12423e77f6538c97b (patch)
treedd3dc1697bfb30baa8e06dca0f50ffc3f313b361 /arch/arm64/boot/dts/freescale/imx8mq.dtsi
parent1fb98e9584460b1c81a1cbdb01d70df232017597 (diff)
ARM64: dts: freescale: imx8mm/8mq: update new compatible name for ecspi and sdma
Add new 'imx6ul-ecspi' compatible name for ecspi and new 'imx8mq-sdma' name for sdma since on i.mx8mm/mq chip fix ecspi errata. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi')
-rwxr-xr-xarch/arm64/boot/dts/freescale/imx8mq.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5d0e85f072fe..9c7fc9d18814 100755
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -671,7 +671,7 @@
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
@@ -683,7 +683,7 @@
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
@@ -695,7 +695,7 @@
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mq-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,