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authorPeter Chen <peter.chen@nxp.com>2019-01-28 15:20:39 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:04:01 +0800
commit370e4a3bef0c996e7bf7fd1717d5974215b7b053 (patch)
tree018a3718fa38b1960101bbfd71583d573cb0ee76 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts
parent8e9d597ea47941d44788b6e68b9f4c2b386e6e1b (diff)
ARM64: dts: imx8qm-mek: enable USB2
Enable both USB2 controller and PHY. Signed-off-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-mek.dts21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index ae408b67d707..32ad12a5bc2f 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -76,6 +76,21 @@
status = "okay";
};
+&usbphy1 {
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ power-active-high;
+ disable-over-current;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -135,6 +150,12 @@
>;
};
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041