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authorRichard Zhu <hongxing.zhu@nxp.com>2019-01-25 18:01:44 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:03:54 +0800
commit3a4a0b052014e3470815a869e2d1693a9e0c5b95 (patch)
tree777e1765ac6c4d7eeb104d5c843563d3b53a9257 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts
parentb02e0dfef83a2fb3e4464c61128ea2d17d325c28 (diff)
ARM64: dts: add the hsio pcie support for imx8qm/qxp
Add the hsio pcie support for imx8qm/qxp. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-mek.dts17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 7b5541e191a8..6660964ffee8 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -67,6 +67,15 @@
};
};
+&pciea{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pciea>;
+ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+ clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
+ ext_osc = <1>;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -114,6 +123,14 @@
>;
};
+ pinctrl_pciea: pcieagrp{
+ fsl,pins = <
+ IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021
+ IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
+ IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041