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authorFugang Duan <fugang.duan@nxp.com>2019-07-29 14:06:39 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:05:17 +0800
commit458f4e39808feaeae0b6401190643a426f3ce2fe (patch)
tree2b006f484f0ea8ffaa89841ff2cc484d40d349f7 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts
parent098d9014307ec9963ad1455c7437bf0718c99e2c (diff)
arm64: dts: imx8qm-mek: add lpuart ports
Add lpuart1/2/3 ports for MEK board. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-mek.dts41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 8aa62c5d1bd1..fd71cda5d744 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -103,6 +103,24 @@
status = "okay";
};
+&lpuart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&lpuart2 { /* Dbg console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "disabled";
+};
+
+&lpuart3 { /* MKbus */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "disabled";
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -331,6 +349,29 @@
>;
};
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020
+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020
+ IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
+ IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
+ IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020
+ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
+ >;
+ };
+
pinctrl_pciea: pcieagrp{
fsl,pins = <
IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021