diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-09-06 10:53:36 -0400 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:35 +0800 |
| commit | 596b29d461786e8fdb31b61cc98a12fe53ecb90d (patch) | |
| tree | d47a44d17a1849ccb01e20f51123c6cabbd93136 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts | |
| parent | 9761c20023cc014311eb0b03eddd9f5e01e81df4 (diff) | |
arm64: dts: fix 8qm pcie boot hang
Make sure that the REF CLK is turned on.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 672ffd2b703c..02ddde1f3eac 100755 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -588,6 +588,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pciea>; reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; ext_osc = <1>; status = "okay"; }; @@ -613,6 +614,9 @@ }; &sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; ext_osc = <1>; status = "okay"; }; @@ -1054,10 +1058,17 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 >; }; + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 |