diff options
| author | Peter Chen <peter.chen@nxp.com> | 2019-08-19 14:48:49 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:32 +0800 |
| commit | b02dbe4a3b250c5b9ffc09c5b73fb42a4530e791 (patch) | |
| tree | 242e2aa3e1317a52d6f2105c940b82c9535e8d40 /arch/arm64/boot/dts/freescale/imx8qm-mek.dts | |
| parent | 1ace3276407c0a7d2dfa8ef0eb798e5c3db46658 (diff) | |
ARM64: dts: imx8qm-mek: add USBOTG3 support
It is a USB3 port which uses Cadence IP.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 6d6a01070761..7f66f95e3beb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -448,6 +448,16 @@ status = "okay"; }; +&usb3phynop1 { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; |