diff options
| author | Zhou Peng <eagle.zhou@nxp.com> | 2019-08-27 10:45:37 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:01 +0800 |
| commit | b54433f21b34cff9a64673f414c6cbf389ecc8a5 (patch) | |
| tree | e71580d7f2843b751533ba372b3dce173ac6731e /arch/arm64/boot/dts/freescale/imx8qm-mek.dts | |
| parent | f2a981c62f7a4ffcb6dec3f9f0a34fca8eb73973 (diff) | |
arm64: dts: imx8qm: add vpu decoder and encoder
enable vpu decoder and encoder
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-mek.dts')
| -rwxr-xr-x[-rw-r--r--] | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 5060621b5685..d515381f824a 100644..100755 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -1198,3 +1198,61 @@ }; }; }; + +&mu_m0{ + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu1_m0{ + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mu2_m0{ + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&vpu_decoder { + compatible = "nxp,imx8qm-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d080000>; + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + compatible = "nxp,imx8qm-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1080>; + fps-max = <120>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>, + <&pd IMX_SC_R_VPU>, <&pd IMX_SC_R_VPU_MU_1>, <&pd IMX_SC_R_VPU_MU_2>; + power-domain-names = "vpuenc", "vpu", "vpumu1", "vpumu2"; + status = "okay"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10A0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; |