diff options
author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-08-27 16:59:04 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:06 +0800 |
commit | 4bc67e56ba09ca37d09ed3ba1f0a5342f8da959b (patch) | |
tree | 082df9839be8b245b35269beb01940d007628fce /arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | |
parent | bd2919dfb81bc11ce382e4ff84f2ca6901aa67cf (diff) |
arm64: dts: imx8qm: fix hsio phyx2 lpcg power domain
It should be SERDES_0.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index ece43350dadb..41ad18166653 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -39,7 +39,7 @@ bit-offset = <0 4>; clock-output-names = "hsio_phyx2_pclk_0", "hsio_phyx2_pclk_1"; - power-domains = <&pd IMX_SC_R_PCIE_A>; + power-domains = <&pd IMX_SC_R_SERDES_0>; }; phyx1_lpcg: clock-controller@5f090000 { |