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authorLiu Ying <victor.liu@nxp.com>2019-11-14 15:49:47 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:10:04 +0800
commitbcb66a5be4a619e531cb016c1093e582274d257f (patch)
treeb7696e5d079c33f2b5af3e4d135e41b50df0e77e /arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
parentc7dcf1ef9edb523fe67fe122427b126ac3cdf199 (diff)
arm64: imx8qm-ss-lvds.dtsi: Add lvds0/1_pwm_lpcg clocks support
This patch adds lvds0/1_pwm_lpcg clocks support for i.MX8QM LVDS subsystem device tree. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
index 77ec06a441fb..ff54354fbd4c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
@@ -28,6 +28,18 @@
power-domains = <&pd IMX_SC_R_LVDS_0>;
};
+ lvds0_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds0_pwm_lpcg_clk",
+ "lvds0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ };
+
lvds0_i2c0_lpcg: clock-controller@56243010 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x56243010 0x4>;
@@ -169,6 +181,18 @@
power-domains = <&pd IMX_SC_R_LVDS_1>;
};
+ lvds1_pwm_lpcg: clock-controller@5724300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5724300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds1_pwm_lpcg_clk",
+ "lvds1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ };
+
lvds1_i2c0_lpcg: clock-controller@57243010 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x57243010 0x4>;