diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2020-08-17 14:43:03 +0800 |
|---|---|---|
| committer | Clark Wang <xiaoning.wang@nxp.com> | 2020-08-17 15:04:37 +0800 |
| commit | d6125908c4458acafcf8e34bb3f74476f75cddf3 (patch) | |
| tree | 926b293fa9819581ac51a2bad09939d1d846f8fb /arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | |
| parent | b287e45d990688b71ac4e51ccd4b67a36dea71ff (diff) | |
MLK-24506 arm64: dts: imx8qm: update i2c nodes of lvds0/1
Fix the reg size of i2c1_lvds0/1 from 0x4000 to 0x1000.
Add i2c0_lvds0/1 nodes which are set disabled by default.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 32 |
1 files changed, 30 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi index 788250766632..03786f8e0f5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -163,9 +163,23 @@ status = "disabled"; }; + i2c0_lvds0: i2c@56246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + i2c1_lvds0: i2c@56247000 { compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x56247000 0x4000>; + reg = <0x56247000 0x1000>; interrupts = <9>; interrupt-parent = <&irqsteer_lvds0>; clocks = <&lvds0_i2c0_lpcg 0>, @@ -336,9 +350,23 @@ status = "disabled"; }; + i2c0_lvds1: i2c@57246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + i2c1_lvds1: i2c@57247000 { compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x57247000 0x4000>; + reg = <0x57247000 0x1000>; interrupts = <9>; interrupt-parent = <&irqsteer_lvds1>; clocks = <&lvds1_i2c0_lpcg 0>, |