diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-12-03 20:25:21 +0800 |
|---|---|---|
| committer | Liu Ying <victor.liu@nxp.com> | 2019-12-04 13:26:55 +0800 |
| commit | bc13a402c691ebb75b1307ca2c5fe678b5bc1b46 (patch) | |
| tree | 02fab8f56467efb485c495af1a7e0f860ca16c6e /arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | |
| parent | 545c6201daf46624a3834a7014971a6c32b2073d (diff) | |
LF-95-2 arm64: imx8qm-ss-mipi.dtsi: Correct MIPI CSR address and size
The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address. However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs. This patch corrects the MIPI CSR
start address and chooses a sensible size, which makes sure all exposed
registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi index 9a9c827d8a91..91397ad49bf5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi @@ -118,9 +118,9 @@ status = "disabled"; }; - mipi0_csr: csr@56220000 { + mipi0_csr: csr@56221000 { compatible = "syscon"; - reg = <0x56220000 0x10000>; + reg = <0x56221000 0x240>; }; mipi0_dphy: dphy@56228300 { @@ -284,9 +284,9 @@ status = "disabled"; }; - mipi1_csr: csr@57220000 { + mipi1_csr: csr@57221000 { compatible = "syscon"; - reg = <0x57220000 0x10000>; + reg = <0x57221000 0x240>; }; mipi1_dphy: dphy@57228300 { |