diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-06-11 13:27:53 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:36 +0800 |
| commit | 3027b04eab96c8eca76cee1543946b1365dfeeb9 (patch) | |
| tree | ea34b1985d43d4ca5d54c93ad4eb169f8b36529b /arch/arm64/boot/dts/freescale/imx8qm.dtsi | |
| parent | f6e276ee872d99f318ad878525c19c2c59c84a8e (diff) | |
arm64: dts: imx8qm: Add A53 OPP table
Add A53 OPP table to support cpu-freq.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index a03be6d07576..245412a0146a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -68,8 +68,10 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; + clocks = <&clk IMX_A53_CLK>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -77,8 +79,10 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; + clocks = <&clk IMX_A53_CLK>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -86,8 +90,10 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; + clocks = <&clk IMX_A53_CLK>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -95,8 +101,10 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; + clocks = <&clk IMX_A53_CLK>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -127,6 +135,36 @@ }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |