diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-06-11 13:06:31 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:36 +0800 |
| commit | f6e276ee872d99f318ad878525c19c2c59c84a8e (patch) | |
| tree | 00a244c16a0a5fd2a1b6918d8a2034e610f33a9e /arch/arm64/boot/dts/freescale/imx8qm.dtsi | |
| parent | 704919bc18f13447460987e02a3d05487b865c62 (diff) | |
arm64: dts: imx8qm: Add thermal zone node
This patch adds i.MX8QM thermal zones support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 1358bb6fa33e..a03be6d07576 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/pads-imx8qm.h> #include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -69,6 +70,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -77,6 +79,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -85,6 +88,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -93,6 +97,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A72_0: cpu@100 { @@ -101,6 +106,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&A72_L2>; + #cooling-cells = <2>; }; A72_1: cpu@101 { @@ -109,6 +115,7 @@ reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&A72_L2>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -222,6 +229,96 @@ rtc: rtc { compatible = "fsl,imx8qm-sc-rtc"; }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qm-sc-thermal"; + tsens-num = <5>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A53>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; /* sorted in register address */ |