diff options
| author | Guoniu.zhou <guoniu.zhou@nxp.com> | 2019-04-25 15:26:40 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:19 +0800 |
| commit | 056478146c13429c6e58b8dbc788d054a15f01cd (patch) | |
| tree | 9e6fe676e4c28b6fb4a0aa8fdabb7674b18cf6b8 /arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | |
| parent | 5f96d0fe49c0159f60e6e75e437e11a369027ac3 (diff) | |
arm64: dts: add parallel capture subsystem device node
Add parallel capture subsystem device nodes for imx8qxp platform.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-mek.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 9b654659c35c..39dc5794d900 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -214,6 +214,33 @@ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; fsl,txs-rxm; }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi_lpcg IMX_PI_LPCG_PI0_MISC_CLK>; + assigned-clocks = <&pi_lpcg IMX_PI_LPCG_PI0_MISC_CLK>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; }; &cm40_intmux { @@ -604,10 +631,20 @@ status = "okay"; }; +&pi_lpcg { + status = "okay"; +}; + &irqsteer_csi0 { status = "okay"; }; +&isi_4 { + interface = <6 0 2>; + parallel_csi; + status = "okay"; +}; + &mipi_csi_0 { #address-cells = <1>; #size-cells = <0>; @@ -623,6 +660,23 @@ }; }; +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &i2c_mipi_csi0 { #address-cells = <1>; #size-cells = <0>; @@ -841,6 +895,26 @@ IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 >; }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 + IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 + IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 + IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 + IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 + IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 + IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 + IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 + + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 + IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 + IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; }; &adma_dsp { |