diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-18 18:39:35 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:01 +0800 |
| commit | 464d1ca6475866a3d76148c5a17a04b9a3f4cca9 (patch) | |
| tree | 603cb7c57947df76e3f4388d0cc7b67451e5985f /arch/arm64/boot/dts/freescale/imx8qxp.dtsi | |
| parent | 937b511d2f45af2ede28068dcf7551a45835a2d1 (diff) | |
arm64: dts: imx8: cm40: move into a separate ss dtsi
move cm40 changes into a separate ss dtsi
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 61 |
1 files changed, 1 insertions, 60 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 13df7a479148..fa8d6fc20b1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -262,66 +262,6 @@ fsl,heap-id = <0>; }; - cm40_subsys: bus@34000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x34000000 0x0 0x34000000 0x4000000>; - - cm40_ipg_clk: clock-cm40-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <132000000>; - clock-output-names = "cm40_ipg_clk"; - }; - - cm40_i2c: i2c@37230000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x37230000 0x1000>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&cm40_intmux>; - clocks = <&cm40_i2c_lpcg 0>, - <&cm40_i2c_lpcg 1>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_M4_0_I2C>; - status = "disabled"; - }; - - cm40_i2c_lpcg: clock-controller@37630000 { - compatible = "fsl,imx8qxp-lpcg"; - reg = <0x37630000 0x1000>; - #clock-cells = <1>; - clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, - <&cm40_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "cm40_lpcg_i2c_clk", - "cm40_lpcg_i2c_ipg_clk"; - power-domains = <&pd IMX_SC_R_M4_0_I2C>; - }; - - cm40_intmux: intmux@37400000 { - compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; - reg = <0x37400000 0x1000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - clocks = <&cm40_ipg_clk>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; - status = "disabled"; - }; - }; - gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; @@ -358,6 +298,7 @@ }; /* sorted in register address */ + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-dc.dtsi" #include "imx8-ss-lvds.dtsi" |