diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-18 18:22:43 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:01 +0800 |
| commit | 937b511d2f45af2ede28068dcf7551a45835a2d1 (patch) | |
| tree | 07cf4653ef7f84461d26d33022aff90fb57e69a3 /arch/arm64/boot/dts/freescale/imx8qxp.dtsi | |
| parent | cdd5694363e9ac7e0ec1e45d389aa856ff6ad1b7 (diff) | |
arm64: dts: imx8: cm40: fully switched to new clk binding
fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index e3b73bb65568..13df7a479148 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -268,10 +268,11 @@ #size-cells = <1>; ranges = <0x34000000 0x0 0x34000000 0x4000000>; - cm40_lpcg: clock-controller@375d0000 { - compatible = "fsl,imx8qxp-lpcg-cm40"; - reg = <0x375d0000 0x70000>; - #clock-cells = <1>; + cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; }; cm40_i2c: i2c@37230000 { @@ -279,15 +280,27 @@ reg = <0x37230000 0x1000>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&cm40_intmux>; - clocks = <&cm40_lpcg IMX_CM40_LPCG_I2C_CLK>, - <&cm40_lpcg IMX_CM40_LPCG_I2C_IPG_CLK>; + clocks = <&cm40_i2c_lpcg 0>, + <&cm40_i2c_lpcg 1>; clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX_CM40_I2C_DIV>; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_M4_0_I2C>; status = "disabled"; }; + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; + cm40_intmux: intmux@37400000 { compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; reg = <0x37400000 0x1000>; @@ -302,7 +315,7 @@ interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; - clocks = <&clk IMX_CM40_IPG_CLK>; + clocks = <&cm40_ipg_clk>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; status = "disabled"; |