diff options
| author | Xianzhong <xianzhong.li@nxp.com> | 2019-01-29 02:21:39 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:03:59 +0800 |
| commit | 93f723834198e09a4af43d3d4c4f63c9710a6618 (patch) | |
| tree | f32bcf443e9468300d836b3c8c22d8774d881933 /arch/arm64/boot/dts/freescale/imx8qxp.dtsi | |
| parent | 01ea60eb25ea694ba169108a56e681484bbfb924 (diff) | |
ARM64: dts: freescale: imx8qxp-mek: add gpu device
Add gpu in device tree:
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 39619a326646..2547dc7c1ddf 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -294,6 +294,26 @@ }; }; + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x53100000 0 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_GPU0_CORE_CLK>, <&clk IMX_GPU0_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_GPU0_CORE_CLK>, <&clk IMX_GPU0_SHADER_CLK>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + /* sorted in register address */ #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" |