diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2019-01-21 16:56:42 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:03:53 +0800 |
| commit | c607df59ffdf183c4af79dd9a54bb74c63e3cb6f (patch) | |
| tree | a1d13c77c76bc7f6c3115ab52308f0307e30be77 /arch/arm64/boot/dts/freescale/imx8qxp.dtsi | |
| parent | 5b2c6f40bdcf66ad6d31f0161c7128e6ec999e67 (diff) | |
arm64: dts: imx8qxp: add i2c and intmux in cm40
Add i2c and intmux device which are in cm40 subsystem.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 294190a83815..6efd18d7e768 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -211,6 +211,53 @@ fsl,heap-id = <0>; }; + cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + + cm40_lpcg: clock-controller@375d0000 { + compatible = "fsl,imx8qxp-lpcg-cm40"; + reg = <0x375d0000 0x70000>; + #clock-cells = <1>; + }; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm40_intmux>; + clocks = <&cm40_lpcg IMX_CM40_LPCG_I2C_CLK>, + <&cm40_lpcg IMX_CM40_LPCG_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_CM40_I2C_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_intmux: intmux@37400000 { + compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; + }; + /* sorted in register address */ #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" |