diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-18 22:37:42 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:05 +0800 |
| commit | ce1b32cea9b26c681856002a6b33ba0320fea48e (patch) | |
| tree | 327b79aa2078c5235eb81420a5ffb90f70b29207 /arch/arm64/boot/dts/freescale/imx8qxp.dtsi | |
| parent | bee78ead959180bdd4e901f743b17e0b61e3ce57 (diff) | |
arm64: dts: imx8: gpu: fully switched to new clk binding
fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 45 |
1 files changed, 27 insertions, 18 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 4127b391829e..ee452eab7ce1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -269,16 +269,33 @@ fsl,heap-id = <0>; }; - gpu_3d0: gpu@53100000 { - compatible = "fsl,imx8-gpu"; - reg = <0x0 0x53100000 0 0x40000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX_GPU0_CORE_CLK>, <&clk IMX_GPU0_SHADER_CLK>; - clock-names = "core", "shader"; - assigned-clocks = <&clk IMX_GPU0_CORE_CLK>, <&clk IMX_GPU0_SHADER_CLK>; - assigned-clock-rates = <700000000>, <850000000>; - power-domains = <&pd IMX_SC_R_GPU_0_PID0>; - status = "disabled"; + gpu_subsys: bus@53100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53100000 0x0 0x53100000 0x40000>; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x53100000 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; }; rpmsg: rpmsg{ @@ -296,14 +313,6 @@ status = "disabled"; }; - imx8_gpu_ss: imx8_gpu_ss { - compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; - cores = <&gpu_3d0>; - reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; - reg-names = "phys_baseaddr", "contiguous_mem"; - status = "disabled"; - }; - /* sorted in register address */ #include "imx8-ss-cm40.dtsi" #include "imx8-ss-vpu.dtsi" |