diff options
| author | Peng Fan <peng.fan@nxp.com> | 2021-10-12 17:10:59 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:51:46 +0800 |
| commit | 7976a19341930e4e3fd362f9a7ffe151b7a62d79 (patch) | |
| tree | f7d99f69cd370eaddc731c9de168c1bb42044d93 /arch/arm64/boot/dts/freescale/imx8ulp.dtsi | |
| parent | bd51db3009580be82a139b7a35dc469e17e7080d (diff) | |
LF-4802 arm64: dts: imx8ulp: add ND dts
Add ND dts for running at 1.0V, also update common dtsi to fix I3C
PLL3 settings has been moved to bootloader, so not touch in dtsi to
avoid people update this pll3 freq to avoid hang, because nic
sources from it.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8ulp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 18345fb21bf6..2e36ae2b0c62 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -391,12 +391,8 @@ clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; clock-names = "rosc", "sosc", "frosc", "lposc"; #clock-cells = <1>; - assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3>, - <&cgc1 IMX8ULP_CLK_SPLL3_PFD1>, - <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; - assigned-clock-rates = <540672000>, - <540672000>, - <12288000>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + assigned-clock-rates = <12288000>; }; pcc3: clock-controller@292d0000 { @@ -471,8 +467,8 @@ <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "pclk", "fast_clk", "slow_clk"; assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>; - assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; - assigned-clock-rates = <48000000>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; status = "disabled"; }; |