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authorLiu Ying <victor.liu@nxp.com>2020-04-16 11:59:10 +0800
committerLiu Ying <victor.liu@nxp.com>2020-04-17 16:30:44 +0800
commit10c15cd0cb769a63ea2e2055d417e6497fa95b61 (patch)
treeca6cfea7a91eb432c806c5a6ba93aed10bb54d60 /arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi
parent993497d966b434f5bb72e84d3b2f2f730ad588ae (diff)
LF-1232-10 arm64: dts: imx8x-mek: Introduce DPU LCDIF include file
This patch introduces DPU LCDIF dts include file, so that it may be included in some dts files as needed. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi75
1 files changed, 75 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi
new file mode 100644
index 000000000000..172c0d2734be
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&lcdif_backlight>;
+ status = "okay";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ display@disp1 {
+ compatible = "fsl,imx-lcdif-mux-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+ clock-names = "bypass_div", "pixel";
+ assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+ assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
+ fsl,lcdif-mux-regs = <&lcdif_mux_regs>;
+ fsl,interface-pix-fmt = "rgb666";
+ power-domains = <&pd IMX_SC_R_LCD_0>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&dpu_disp1_lcdif>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+};
+
+&dpu_disp1_lcdif {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&iomuxc {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000
+ >;
+ };
+};
+
+&sai1 {
+ status = "disabled";
+};
+
+&esai0 {
+ status = "disabled";
+};
+
+&lpuart1 {
+ status = "disabled";
+};