diff options
| author | Leonard Crestez <leonard.crestez@nxp.com> | 2019-11-07 18:29:47 +0200 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:11:43 +0800 |
| commit | 38395e17e73da43430fee47cb6ce7a582f618c69 (patch) | |
| tree | 08bfd1a5e981512d1dbc053d3ed3a737d25f28e7 /arch/arm64/boot/dts/freescale/s32v234-sbc.dts | |
| parent | 819b2eb7cc3c7324508ba76bd59025f350ae9ae6 (diff) | |
arm64: dts: s32v234: Initial ethernet support
Add fec node to SOC dtsi and enable on s32v234-sbc board
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32v234-sbc.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234-sbc.dts | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts index 1a306892a758..7997556164ec 100644 --- a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts +++ b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts @@ -22,6 +22,22 @@ }; }; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + &siul2 { status = "okay"; @@ -31,6 +47,33 @@ * Manual states. */ + pinctrl_enet: enetgrp { + fsl,pins = < + S32V234_PAD_PC13__MDC + S32V234_PAD_PC14__MDIO_OUT + S32v234_PAD_PC14__MDIO_IN + S32V234_PAD_PC15__TXCLK_OUT + S32V234_PAD_PC15__TXCLK_IN + S32V234_PAD_PD0__RXCLK_OUT + S32V234_PAD_PD0__RXCLK_IN + S32V234_PAD_PD1__RX_D0_OUT + S32V234_PAD_PD1__RX_D0_IN + S32V234_PAD_PD2__RX_D1_OUT + S32V234_PAD_PD2__RX_D1_IN + S32V234_PAD_PD3__RX_D2_OUT + S32V234_PAD_PD3__RX_D2_IN + S32V234_PAD_PD4__RX_D3_OUT + S32V234_PAD_PD4__RX_D3_IN + S32V234_PAD_PD4__RX_DV_OUT + S32V234_PAD_PD4__RX_DV_IN + S32V234_PAD_PD7__TX_D0_OUT + S32V234_PAD_PD8__TX_D1_OUT + S32V234_PAD_PD9__TX_D2_OUT + S32V234_PAD_PD10__TX_D3_OUT + S32V234_PAD_PD11__TX_EN_OUT + >; + }; + pinctrl_uart0: uart0grp { fsl,pins = < 12 PAD_CTL_UART_TX |