diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2018-03-14 16:08:30 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:09 +0800 |
| commit | 11c7d1a536fa76397dec07183ff8bbda2dda3a99 (patch) | |
| tree | 42ca0fb7375e15fca3e9a03a55b0277dfafea1c4 /arch/arm64/boot/dts/freescale | |
| parent | 5928d3b11e3be209d1894db1c798608c149d51e5 (diff) | |
MLK-17800-2: ARM64: dts: Remove the esai workaround for imx8qxp B0
Fixes commit 175fcc2bd433 ("MLK-15004-4: ASoC: fsl_esai: esai
workaround for imx8qxp Rev1")
The hardware issue that ESAI dma event is not connected to
EDMA correctly is fixed in B0.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts | 3 | ||||
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts index ea5a7d791fb0..05cbbdb7fc29 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts @@ -107,7 +107,7 @@ }; &esai0 { - compatible = "fsl,imx8qxp-v1-esai"; + compatible = "fsl,imx8qm-esai"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esai0>; assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, @@ -117,7 +117,6 @@ <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; - dmas = <&edma2 23 0 3>, <&edma2 21 0 2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts index 4c968208d031..0b286d2a86e2 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts @@ -153,7 +153,7 @@ }; &esai0 { - compatible = "fsl,imx8qxp-v1-esai"; + compatible = "fsl,imx8qm-esai"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esai0>; assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, @@ -163,7 +163,6 @@ <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; - dmas = <&edma2 23 0 3>, <&edma2 21 0 2>; status = "okay"; }; |