MLK-22921-4 ARM64: dts: imx8qxp/qm: add lpspi dts files

Add lpspi mater and slave dts files for imx8qxp/qm platforms.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

6 files changed, 202 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 0e3ad51b0584..c1f2ee97203d 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \
 			  imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \
 			  imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \
 			  imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \
+			  imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \
 			  imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb
@@ -52,5 +53,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640
 			  imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb \
 			  imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb imx8qxp-lpddr4-val-a0.dtb \
 			  imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \
+			  imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \
 			  imx8qxp-lpddr4-val-spdif.dtb imx8dxp-lpddr4-val.dtb imx8qxp-17x17-val.dtb \
 			  imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 6feb7d1129e6..dab01d97a3ef 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -22,6 +22,8 @@ dma_subsys: bus@5a000000 {
 	lpspi0: spi@5a000000 {
 		compatible = "fsl,imx7ulp-spi";
 		reg = <0x5a000000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
 		clocks = <&spi0_lpcg 0>,
@@ -36,6 +38,8 @@ dma_subsys: bus@5a000000 {
 	lpspi2: spi@5a020000 {
 		compatible = "fsl,imx7ulp-spi";
 		reg = <0x5a020000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
 		clocks = <&spi2_lpcg 0>,
@@ -47,6 +51,22 @@ dma_subsys: bus@5a000000 {
 		status = "disabled";
 	};
 
+	lpspi3: spi@5a030000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x5a030000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&spi3_lpcg 0>,
+			 <&spi3_lpcg 1>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <60000000>;
+		power-domains = <&pd IMX_SC_R_SPI_3>;
+		status = "disabled";
+	};
+
 	lpuart0: serial@5a060000 {
 		reg = <0x5a060000 0x1000>;
 		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
@@ -197,6 +217,18 @@ dma_subsys: bus@5a000000 {
 		power-domains = <&pd IMX_SC_R_SPI_2>;
 	};
 
+	spi3_lpcg: clock-controller@5a430000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a430000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "spi3_lpcg_clk",
+				     "spi3_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_SPI_3>;
+	};
+
 	uart0_lpcg: clock-controller@5a460000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5a460000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts
new file mode 100644
index 000000000000..302cc251e3df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018~2019 NXP
+ */
+
+#include "imx8qm-lpddr4-val-lpspi.dts"
+
+/delete-node/&spidev0;
+
+&pinctrl_lpspi3 {
+	fsl,pins = <
+		IMX8QM_SPI3_SCK_DMA_SPI3_SCK		0x600004c
+		IMX8QM_SPI3_SDO_DMA_SPI3_SDO		0x600004c
+		IMX8QM_SPI3_SDI_DMA_SPI3_SDI		0x600004c
+		IMX8QM_SPI3_CS0_DMA_SPI3_CS0		0x600004c
+	>;
+};
+
+&lpspi3 {
+	#address-cells = <0>;
+	pinctrl-0 = <&pinctrl_lpspi3>;
+	/delete-property/ cs-gpios;
+	spi-slave;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts
new file mode 100644
index 000000000000..da0682d0eaab
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2019 NXP
+ */
+
+#include "imx8qm-lpddr4-val.dts"
+
+&iomuxc {
+	pinctrl_lpspi0: lpspi0grp {
+		fsl,pins = <
+			IMX8QM_SPI0_SCK_DMA_SPI0_SCK		0x600004c
+			IMX8QM_SPI0_SDO_DMA_SPI0_SDO		0x600004c
+			IMX8QM_SPI0_SDI_DMA_SPI0_SDI		0x600004c
+		>;
+	};
+
+	pinctrl_lpspi0_cs: lpspi0cs {
+		fsl,pins = <
+			IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05		0x21
+		>;
+	};
+
+	pinctrl_lpspi3: lpspi3grp {
+		fsl,pins = <
+			IMX8QM_SPI3_SCK_DMA_SPI3_SCK		0x600004c
+			IMX8QM_SPI3_SDO_DMA_SPI3_SDO		0x600004c
+			IMX8QM_SPI3_SDI_DMA_SPI3_SDI		0x600004c
+			IMX8QM_SPI3_CS0_DMA_SPI3_CS0		0x600004c
+		>;
+	};
+};
+
+&lpspi0 {
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
+	cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	flash: at45db041e@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "atmel,at45", "atmel,dataflash";
+		spi-max-frequency = <5000000>;
+		reg = <0>;
+	};
+};
+
+&lpspi3 {
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi3>;
+	status = "okay";
+
+	spidev0: spi@0 {
+		reg = <0>;
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <30000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts
new file mode 100644
index 000000000000..ef997e2f9361
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2019 NXP
+ */
+
+#include "imx8qxp-lpddr4-val-lpspi.dts"
+
+/delete-node/&spidev0;
+
+&pinctrl_lpspi2 {
+	fsl,pins = <
+		IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK		0x600004c
+		IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO		0x600004c
+		IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI		0x600004c
+		IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0		0x600004c
+	>;
+};
+
+&lpspi2 {
+	#address-cells = <0>;
+	pinctrl-0 = <&pinctrl_lpspi2>;
+	/delete-property/ cs-gpios;
+	spi-slave;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts
new file mode 100644
index 000000000000..bc4535647fc4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2019 NXP
+ */
+
+#include "imx8qxp-lpddr4-val.dts"
+
+&iomuxc {
+	pinctrl_lpspi0: lpspi0grp {
+		fsl,pins = <
+			IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK		0x600004c
+			IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO		0x600004c
+			IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI		0x600004c
+		>;
+	};
+
+	pinctrl_lpspi0_cs: lpspi0cs {
+		fsl,pins = <
+			IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08	0x21
+		>;
+	};
+
+	pinctrl_lpspi2: lpspi2grp {
+		fsl,pins = <
+			IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK		0x600004c
+			IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO		0x600004c
+			IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI		0x600004c
+			IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0		0x600004c
+		>;
+	};
+};
+
+&lpspi0 {
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
+	cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	flash: at45db041e@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "atmel,at45", "atmel,dataflash";
+		spi-max-frequency = <5000000>;
+		reg = <0>;
+	};
+};
+
+&lpspi2 {
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi2>;
+	status = "okay";
+
+	spidev0: spi@0 {
+		reg = <0>;
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <10000000>;
+	};
+};