diff options
| author | Han Xu <han.xu@nxp.com> | 2019-11-13 22:11:02 -0600 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:57 +0800 |
| commit | 334cf0a275ea1b4ecec34f7b5ffe0ef0a72c1914 (patch) | |
| tree | 1238a7261858808aa652c7c2f058919bd58a3206 /arch/arm64/boot/dts/freescale | |
| parent | 7085cfb62d9b501e503811eedfaddc9ad69193c6 (diff) | |
arm64: dts: add flexspi in iMX8MN EVK dts
add flexspi support in iMX8MN EVK dts
Signed-off-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 16 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 15 |
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index b19c54284d97..1ab6a53178a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -484,6 +484,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &ecspi2 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index c361b19b6764..3db4c151bbfb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -849,6 +849,21 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-flexspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi-mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; |