MLK-24334-9: arch: arm64: dts: imx8dxl: unify adma_lcdif

Currently, the adma_lcdif and it's related nodes are duplicated in 8qxp
and 8dxl dts files. Since it's the same subsystem, move these nodes into
generic files, so that both 8qxp and 8dxl dts files can use them.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

9 files changed, 80 insertions, 152 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 5e2cc2787716..e33c2080ce3c 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -583,4 +583,29 @@ dma_subsys: bus@5a000000 {
 		compatible = "fsl,i2c-rpbus";
 		status = "disabled";
 	};
+
+	adma_pwm: pwm@5a190000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x5a190000 0x1000>;
+		clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
+		status = "disabled";
+	};
+
+	adma_pwm_lpcg: clock-controller@5a590000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a590000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "adma_pwm_lpcg_clk",
+				     "adma_pwm_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi
new file mode 100644
index 000000000000..4bf058106fec
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+lcdif_subsys: bus@5a180000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x5a180000 0x0 0x5a180000 0x500000>;
+
+	ipg_dma_clk: clock-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <120000000>;
+		clock-output-names = "ipg_dma_clk";
+	};
+
+	lcd_clk_lpcg: clock-controller@5a580000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a580000 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
+			 <&ipg_dma_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LCD_0>;
+	};
+
+	adma_lcdif: lcdif@5a180000 {
+		compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
+		reg = <0x5a180000 0x10000>;
+		clocks = <&lcd_clk_lpcg 0>,
+			 <&lcd_clk_lpcg 1>,
+			 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+		clock-names = "pix", "axi", "disp_axi";
+		assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
+				  <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
+				  <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
+		assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
+					 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
+		assigned-clock-rates = <0>, <24000000>, <804000000>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd IMX_SC_R_LCD_0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index ddd7fe759e7a..ae90a2e139e7 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -228,29 +228,3 @@
 	interrupts =  <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */
 		      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */
 };
-
-&dma_subsys {
-	adma_pwm: pwm@5a190000 {
-		compatible = "fsl,imx8dxl-pwm", "fsl,imx27-pwm";
-		reg = <0x5a190000 0x1000>;
-		clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
-		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
-		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
-		status = "disabled";
-	};
-
-	adma_pwm_lpcg: clock-controller@5a590000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5a590000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "adma_pwm_lpcg_clk",
-				     "adma_pwm_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
-	};
-};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lcdif.dtsi
deleted file mode 100644
index dcd57fa1e184..000000000000
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lcdif.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/*
- * Copyright 2020 NXP
- */
-
-/ {
-	lcdif_subsys: bus@5a180000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x5a180000 0x0 0x5a180000 0x500000>;
-
-		ipg_dma_clk: clock-ipg {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <120000000>;
-			clock-output-names = "ipg_dma_clk";
-		};
-
-		lcd_clk_lpcg: clock-controller@5a580000 {
-			compatible = "fsl,imx8qxp-lpcg";
-			reg = <0x5a580000 0x4>;
-			#clock-cells = <1>;
-			clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
-				 <&ipg_dma_clk>;
-			bit-offset = <0 16>;
-			clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk";
-			power-domains = <&pd IMX_SC_R_LCD_0>;
-		};
-
-		adma_lcdif: lcdif@5a180000 {
-			compatible = "fsl,imx8dxl-lcdif", "fsl,imx28-lcdif";
-			reg = <0x5a180000 0x10000>;
-			clocks = <&lcd_clk_lpcg 0>,
-				 <&lcd_clk_lpcg 1>,
-				 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
-			clock-names = "pix", "axi", "disp_axi";
-			assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
-					  <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
-					  <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
-			assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
-						 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
-			assigned-clock-rates = <0>, <24000000>, <711000000>;
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&pd IMX_SC_R_LCD_0>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index ad6b450ebc31..ceefcfafd388 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -297,6 +297,7 @@
 	#include "imx8-ss-ddr.dtsi"
 	#include "imx8-ss-lsio.dtsi"
 	#include "imx8-ss-hsio.dtsi"
+	#include "imx8-ss-lcdif.dtsi"
 };
 
 #include "imx8dxl-ss-adma.dtsi"
@@ -305,7 +306,6 @@
 #include "imx8dxl-ss-hsio.dtsi"
 #include "imx8dxl-ss-ddr.dtsi"
 #include "imx8dxl-ss-security.dtsi"
-#include "imx8qxp-ss-lcdif.dtsi"
 
 &edma2 {
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
index 096df87e0c99..f1b9b0da5e6d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -74,28 +74,4 @@
 		compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon";
 		reg = <0x5a170000 0x4>;
 	};
-
-	adma_pwm: pwm@5a190000 {
-		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
-		reg = <0x5a190000 0x1000>;
-		clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
-		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
-		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
-		status = "disabled";
-	};
-
-	adma_pwm_lpcg: clock-controller@5a590000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5a590000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "adma_pwm_lpcg_clk",
-				     "adma_pwm_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
-	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi
deleted file mode 100755
index 1f6a55d1c577..000000000000
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/*
- * Copyright 2020 NXP
- */
-
-/ {
-	lcdif_subsys: bus@5a180000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x5a180000 0x0 0x5a180000 0x500000>;
-
-		ipg_dma_clk: clock-ipg {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <120000000>;
-			clock-output-names = "ipg_dma_clk";
-		};
-
-		lcd_clk_lpcg: clock-controller@5a580000 {
-			compatible = "fsl,imx8qxp-lpcg";
-			reg = <0x5a580000 0x4>;
-			#clock-cells = <1>;
-			clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
-				 <&ipg_dma_clk>;
-			bit-offset = <0 16>;
-			clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk";
-			power-domains = <&pd IMX_SC_R_LCD_0>;
-		};
-
-		adma_lcdif: lcdif@5a180000 {
-			compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
-			reg = <0x5a180000 0x10000>;
-			clocks = <&lcd_clk_lpcg 0>,
-				 <&lcd_clk_lpcg 1>,
-				 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
-			clock-names = "pix", "axi", "disp_axi";
-			assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
-					  <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
-					  <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
-			assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
-						 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
-			assigned-clock-rates = <0>, <24000000>, <804000000>;
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&pd IMX_SC_R_LCD_0>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4495863a7c81..89f6f168cd4b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -334,6 +334,7 @@
 	#include "imx8-ss-hsio.dtsi"
 	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-gpu0.dtsi"
+	#include "imx8-ss-lcdif.dtsi"
 };
 
 #include "imx8qxp-ss-adma.dtsi"
@@ -342,7 +343,6 @@
 #include "imx8qxp-ss-hsio.dtsi"
 #include "imx8qxp-ss-img.dtsi"
 #include "imx8qxp-ss-dc.dtsi"
-#include "imx8qxp-ss-lcdif.dtsi"
 #include "imx8qxp-ss-lvds.dtsi"
 #include "imx8qxp-ss-gpu.dtsi"
 
diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi
index 3345ee9c4c4a..73d5cd433191 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi
@@ -87,6 +87,11 @@
 	status = "okay";
 };
 
+&adma_pwm_lpcg {
+	status = "okay";
+};
+
+
 &adma_lcdif {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcdif>;