diff options
author | Olof Johansson <olof@lixom.net> | 2019-06-25 04:30:13 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2019-06-25 04:30:13 -0700 |
commit | 80f7f92c16d591653c54ab487ec5e6157834b22f (patch) | |
tree | cc13a03ac27e7c1a1f30cbaf7ed4a8b216bcfd2b /arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | |
parent | 98d70a5cd929081e605b2983550a893d6540e955 (diff) | |
parent | 9500ff14c4cf0eedf4c5f55175b9046768db5cbd (diff) |
Merge tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for v5.3
* Hi3660 SoC and related boards:
- Added CoreSight trace components
* Hi6220 SoC and related boards:
- Updated CoreSight funnel and replicator using new bindings to fix warning
* tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hi3660: Add CoreSight support
arm64: dts: hi6220: Update coresight DT bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 30f54b77c2f1..651771a73ed6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -11,7 +11,7 @@ / { soc { funnel@f6401000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xf6401000 0 0x1000>; clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; clock-names = "apb_pclk"; @@ -61,7 +61,7 @@ }; replicator { - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; clock-names = "apb_pclk"; @@ -129,7 +129,7 @@ }; funnel@f6501000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xf6501000 0 0x1000>; clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; clock-names = "apb_pclk"; |