diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-09-20 23:01:02 -0700 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2018-11-28 15:17:50 +0000 |
| commit | a758dd2e3a5108ab84c33c1069dd838f866b014e (patch) | |
| tree | 0e41dc99629f87070389b636523a52a15d8a6f3c /arch/arm64/boot/dts/hisilicon | |
| parent | c00e3f8080d1ad8645ba51ae34817df830b44fa2 (diff) | |
arm64: dts: hisilicon: Source SoC clock for UART6
Remove fixed clock and source SoC clock for UART6 for
HiSilicon Hi3670 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 8a0ee4b08886..34a2f0dbc6f7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -187,17 +187,12 @@ #clock-cells = <1>; }; - uart6_clk: clk_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - uart6: serial@fff32000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfff32000 0x0 0x1000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart6_clk &uart6_clk>; + clocks = <&crg_ctrl HI3670_CLK_UART6>, + <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; |