diff options
| author | Ryder Lee <ryder.lee@mediatek.com> | 2018-07-16 22:59:09 +0800 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2018-07-17 09:56:11 +0200 |
| commit | 2b519747ae4859e886c37834d766fe0c7d8d82e2 (patch) | |
| tree | 1bdd8414d34c720d4890abd77eb943770d714ed8 /arch/arm64/boot/dts/mediatek | |
| parent | c0d9f9ad4f7691f033e6e476300edc1fc9e2688e (diff) | |
arm64: dts: mt7622: update a clock property for UART0
The input clock of UART0 should be CLK_PERI_UART0_PD.
Fixes: 13f36c326cef ("arm64: dts: mt7622: turn uart0 clock to real ones")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 7a3bf15b1b84..de2c47bdbe64 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -339,7 +339,7 @@ reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; + <&pericfg CLK_PERI_UART0_PD>; clock-names = "baud", "bus"; status = "disabled"; }; |