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authorYT Shen <yt.shen@mediatek.com>2018-12-03 19:36:00 +0800
committerMatthias Brugger <matthias.bgg@gmail.com>2019-01-09 18:16:07 +0100
commitdb0b58d88d7d1af5ce3e454e397eb461565675c5 (patch)
tree305a5ab2b97ad4f450361be459f903ad1dee74ac /arch/arm64/boot/dts/mediatek
parentd85b9774c8bda4589db7e82d9e347522b82ef57d (diff)
arm64: dts: add mmc nodes for MT2712
Signed-off-by: YT Shen <yt.shen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712e.dtsi34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e9856fef3e72..4f0aa65f1625 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -611,6 +611,40 @@
status = "disabled";
};
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt2712-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
+ <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
+ <&pericfg CLK_PERI_MSDC50_0_EN>;
+ clock-names = "source", "hclk", "bus_clk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt2712-mmc";
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
+ <&topckgen CLK_TOP_AXI_SEL>,
+ <&pericfg CLK_PERI_MSDC30_1_EN>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt2712-mmc";
+ reg = <0 0x11250000 0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_2>,
+ <&topckgen CLK_TOP_AXI_SEL>,
+ <&pericfg CLK_PERI_MSDC30_2_EN>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
ssusb: usb@11271000 {
compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
reg = <0 0x11271000 0 0x3000>,