diff options
| author | Joseph Lo <josephl@nvidia.com> | 2019-01-04 11:06:59 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-02-07 19:03:09 +0100 |
| commit | a1304d352cca26dc80b70c869848d3ea50f6a54f (patch) | |
| tree | 263b84b87274d7d0393b477ccccd5312048ef24f /arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | |
| parent | a5e98b0b371c11bb49be0b661a03a04a5c3b1f44 (diff) | |
arm64: tegra: Enable DFLL clock on Jetson TX1
Enable DFLL clock for Jetson TX1 platform.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 37e3c46e753f..9fad0d27278e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -78,4 +78,25 @@ }; }; }; + + clock@70110000 { + status = "okay"; + + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,sample-rate = <25000>; + + nvidia,pwm-min-microvolts = <708000>; + nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; }; |