diff options
| author | Thierry Reding <treding@nvidia.com> | 2016-06-09 17:50:57 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-07-14 16:20:26 +0200 |
| commit | 237d5cc779bc506205420846f74f02c40d63f08e (patch) | |
| tree | 13756fc37b0f0c3befa38bc9c31f9ba86972a0e6 /arch/arm64/boot/dts/nvidia/tegra210.dtsi | |
| parent | 241f02ba987baa7bb11b820f8f2f9b71785470e8 (diff) | |
arm64: tegra: Add sor1_src clock
The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra210.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 443ecd58de98..c4cfdcf60d26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -186,10 +186,11 @@ reg = <0x0 0x54580000 0x0 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_SOR1>, + <&tegra_car TEGRA210_CLK_SOR1_SRC>, <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, <&tegra_car TEGRA210_CLK_PLL_DP>, <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "source", "parent", "dp", "safe"; resets = <&tegra_car 183>; reset-names = "sor"; pinctrl-0 = <&state_dpaux1_aux>; |