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authorJoseph Lo <josephl@nvidia.com>2019-01-04 11:06:56 +0800
committerThierry Reding <treding@nvidia.com>2019-02-07 19:03:01 +0100
commit2ceed59366b1405914631fc389bd46172b48f95d (patch)
tree2932fb65d7204ebacd09468586e4643ace297b24 /arch/arm64/boot/dts/nvidia/tegra210.dtsi
parentd428f35d959c951244970c5f142616802f39de33 (diff)
arm64: tegra: Add DFLL clock on Tegra210
Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra210.dtsi')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 61d2dbe4ce53..09f4d48fac9c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
@@ -1131,6 +1132,24 @@
#nvidia,mipi-calibrate-cells = <1>;
};
+ dfll: clock@70110000 {
+ compatible = "nvidia,tegra210-dfll";
+ reg = <0 0x70110000 0 0x100>, /* DFLL control */
+ <0 0x70110000 0 0x100>, /* I2C output control */
+ <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+ <0 0x70110200 0 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA210_CLK_DFLL_REF>,
+ <&tegra_car TEGRA210_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ status = "disabled";
+ };
+
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,