diff options
| author | Joseph Lo <josephl@nvidia.com> | 2019-02-01 11:43:47 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-04-12 17:21:50 +0200 |
| commit | 6c00cac1de5e99c5a7cb91bdfcef63987bd7da9f (patch) | |
| tree | 1158d5c8515469f4eaff984de271df77c4413ae6 /arch/arm64/boot/dts/nvidia/tegra210.dtsi | |
| parent | 3056c1ca29393c4aea79d53940c4b06774f9a5ce (diff) | |
arm64: tegra: Add L2 cache topology to Tegra210
Add L2 cache and make it the next level of cache for each of the CPUs.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra210.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 79cedd36ffad..a550c0a4d572 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1372,6 +1372,7 @@ clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2>; }; cpu@1 { @@ -1379,6 +1380,7 @@ compatible = "arm,cortex-a57"; reg = <1>; cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2>; }; cpu@2 { @@ -1386,6 +1388,7 @@ compatible = "arm,cortex-a57"; reg = <2>; cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2>; }; cpu@3 { @@ -1393,6 +1396,7 @@ compatible = "arm,cortex-a57"; reg = <3>; cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2>; }; idle-states { @@ -1409,6 +1413,10 @@ status = "disabled"; }; }; + + L2: l2-cache { + compatible = "cache"; + }; }; timer { |