diff options
| author | Aapo Vienamo <avienamo@nvidia.com> | 2018-08-10 21:08:42 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-08-27 12:27:31 +0200 |
| commit | 918f9671c86b1d4771e9738f9c42abce90194369 (patch) | |
| tree | 64850b0ed2676a8693d502c55f6dbb7fba95ea6a /arch/arm64/boot/dts/nvidia/tegra210.dtsi | |
| parent | 6f90c6f0db83f2be2dcd9f1a07a5238751b3a7f7 (diff) | |
arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4
Use assigned-clock properties to configure pllc4 as the parent clock
for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than
the default pllp and is required by HS200 and HS400 modes.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra210.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0951acc69cc8..14da98ac65e8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1057,6 +1057,11 @@ nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; nvidia,default-tap = <0x2>; nvidia,default-trim = <0x4>; + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_C4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; status = "disabled"; }; @@ -1107,6 +1112,9 @@ nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; nvidia,default-tap = <0x8>; nvidia,default-trim = <0x0>; + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; status = "disabled"; }; |