diff options
| author | Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> | 2019-07-10 16:59:24 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2019-08-05 14:48:56 -0700 |
| commit | ba0411ddd133b34fd715f17b9c0c29027bfa92a8 (patch) | |
| tree | 9e9435d98e10aa79c94f251f2104ec52adfe27f6 /arch/arm64/boot/dts/qcom/sdm845.dtsi | |
| parent | 887e54218183a2665c4dc59aa10477185145fad9 (diff) | |
arm64: dts: sdm845: Add device node for Last level cache controller
Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c8ebe21f7673..40ec8231b585 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1275,6 +1275,13 @@ }; }; + cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; |