diff options
| author | Biju Das <biju.das@bp.renesas.com> | 2019-06-12 15:20:55 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-06-18 12:42:29 +0200 |
| commit | 9e35f49cf7037c3fe3fe4d51aec6d492741cddbe (patch) | |
| tree | 6c0820991200daeaeff7715a3d83e2565d644145 /arch/arm64/boot/dts/renesas/r8a774a1.dtsi | |
| parent | 06a928fb5805d1bb80a87c557ac487b916adc50d (diff) | |
arm64: dts: renesas: r8a774a1: Add dynamic power coefficient
Describe the dynamic power coefficient of A57 and A53 CPUs.
Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774a1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 7d5e19c8cbd5..b437edc04712 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -135,6 +135,7 @@ power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -162,6 +163,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; #cooling-cells = <2>; + dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <560>; |