diff options
| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2019-02-15 12:26:29 +0000 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-03-18 10:33:19 +0100 |
| commit | 12ce412b2cc6aea88c9c93e6303372f72014efc6 (patch) | |
| tree | bb57399400ccc33149c23ed0be832178db5fec79 /arch/arm64/boot/dts/renesas/r8a774c0.dtsi | |
| parent | 191f7dcd1f5ea1f39abc94cece6156c9fa045974 (diff) | |
arm64: dts: renesas: r8a774c0: Fix cpu nodes style
We usually leave a space between "=" and the value of device
tree properties, but unfortunately that was overlooked for the
"clocks" property of cpu@0 and cpu@1.
This patch fixes the spacing with the "clocks" property of
cpu@0 and cpu@1.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774c0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 61a0afb74e63..0bbcaf181262 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -76,7 +76,7 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -87,7 +87,7 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; |