diff options
| author | Gaku Inami <gaku.inami.xh@renesas.com> | 2018-11-08 16:24:55 +0900 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-11-15 06:27:31 -0800 |
| commit | 2250d856b279d992c392170860a78c2482b1859c (patch) | |
| tree | 57fade5305ed79db93087417b859b6763feab6a2 /arch/arm64/boot/dts/renesas/r8a7796.dtsi | |
| parent | b380ae0db6039131fd0ad985b760c5b3f5096dfc (diff) | |
arm64: dts: renesas: Add CPU capacity-dmips-mhz
Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on
dhrystone. The average in 10 times of dhrystone result as follows:
r8a7795 SoC (A57x4 + A53x4)
CPU max-freq dhrystone
---------------------------------
A57 1500 MHz 11470943 lps/s
A53 1200 MHz 4798583 lps/s
r8a7796 SoC (A57x2 + A53x4)
CPU max-freq dhrystone
---------------------------------
A57 1500 MHz 11463526 lps/s
A53 1200 MHz 4793276 lps/s
Based on above, capacity-dmips-mhz values are calculated as follows:
r8a7795 SoC
A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024
A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535
r8a7796 SoC
A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024
A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535
However, since each CPUs have different max frequencies, the final
CPU capacities of A53 are scaled by this difference, the values are
as follows.
[r8a7795 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 <---- CPU capacity of A57
1024
1024
1024
428 <---- CPU capacity of A53
428
428
428
[r8a7796 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 <---- CPU capacity of A57
1024
428 <---- CPU capacity of A53
428
428
428
Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index b12bf73bb03b..369d0bccc651 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -162,6 +162,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -174,6 +175,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -186,6 +188,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_1: cpu@101 { @@ -197,6 +200,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_2: cpu@102 { @@ -208,6 +212,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_3: cpu@103 { @@ -219,6 +224,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; L2_CA57: cache-controller-0 { |