diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-03 14:18:17 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 07:51:06 +0100 |
| commit | 57a4fd420c6e8a04b6a87ff24d34250cd7c48f15 (patch) | |
| tree | cddf252c28b9bc9a55c521bb92e3bb14537e9870 /arch/arm64/boot/dts/renesas/r8a7796.dtsi | |
| parent | d165856de103a6d317a9c9a5782eacd5dc90a9dc (diff) | |
arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
The Cortex-A57 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 1561f20760ec96db ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index dbf82bc6ba64..27f7dd9bd988 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -47,9 +47,8 @@ enable-method = "psci"; }; - L2_CA57: cache-controller@0 { + L2_CA57: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7796_PD_CA57_SCU>; cache-unified; cache-level = <2>; |